High voltage isolation communication devices known in the prior art include optical devices, magnetic devices and capacitive devices. Prior art optical devices typically achieve high voltage isolation by employing LEDs and corresponding photodiodes to transmit and receive light signals, usually require high power levels, and suffer from operational and design constraints when multiple communication channels are required. Prior art magnetic devices typically achieve high voltage isolation by employing opposing inductively-coupled coils, also usually require high power levels (especially when high data rates required), typically require the use of at least three separate integrated circuits or chips, and are susceptible to electromagnetic interference (“EMI”). Prior art capacitive devices typically achieve high voltage isolation by employing multiple pairs of transmitting and receiving electrodes, where for example a first pair of electrodes is employed to transmit and receive data, and a second pair of electrodes is employed to refresh or maintain the transmitted signals.
Some high voltage isolation communication devices, typically employed in power systems, are implemented in high voltage integrated circuits (HVICs) and are configured to provide level shifting and gate drives for high side insulated-gate bipolar transistors (IGBTs). Conventional HVIC gate drives require the use of high voltage transistors to implement high voltage level shift functionality. Such HVIC gate drives usually require the use of complex and expensive high voltage manufacturing processes, such as silicon-on-insulator (SOI) technology, which substitutes a layered silicon-insulator-silicon substrate for a conventional silicon substrate in the semiconductor manufacturing process. The major disadvantages of SOI implementation are increased manufacturing complexity and a significant increase in substrate cost. Furthermore, the cost of using SOI technology scales with the level of high voltage stress between the low and high side of the gate drive, which further increases cost.
What is needed is a high voltage isolation communication device that is small, consumes reduced power, permits data to be communicated at relatively high data rates, has improved high voltage breakdown capabilities, maintains high voltage isolation characteristics during operation, may be built at lower cost, and that is susceptible to being manufactured using conventional CMOS processes.
Further details concerning various aspects of some prior art devices and methods are set forth in U.S. Pat. No. 5,693,971 to Gonzales entitled “Combined trench and field isolation structure for semiconductor devices” dated Dec. 2, 1997; U.S. Pat. No. 6,167,475 to Carr entitled “Data transfer method/engine for pipelining shared memory bus accesses” dated Dec. 26, 2000; U.S. Pat. No. 6,215,377 to Douriet entitled “Low cost wideband RF port structure for microwave circuit packages using coplanar waveguide and BGA I/O format” dated Apr. 10, 2001; U.S. Pat. No. 6,320,532 to Diede entitled “Low power radar level transmitter having reduced ground loop errors” dated Nov. 20, 2001; U.S. Pat. No. 6,489,850 to Heineke et al. entitled “Crosstalk suppression in differential AC coupled multichannel IC amplifiers” dated Dec. 3, 2002; U.S. Pat. No. 6,538,313 to Smith entitled “IC package with integral substrate capacitor” dated Mar. 25, 2003; U.S. Pat. No. 6,574,091 to Heineke et al. entitled “Multi-plate capacitor structure” dated Jun. 3, 2003; U.S. Pat. No. 6,661,079 to Bikulcius entitled “Semiconductor-based spiral capacitor” dated Dec. 9, 2003; U.S. Pat. No. 6,944,009 to Nguyen et al. entitled “Ultra broadband capacitor assembly” dated Sep. 13, 2005; U.S. Pat. No. 7,170,807 to Fazan et al. entitled “Data storage device and refreshing method for use with such device” dated Jan. 30, 2007; U.S. Patent Publication No. 2007/0133,933 to Hoon entitled “Enhanced coplanar waveguide and optical communication module using the same” dated Jun. 14, 2007; U.S. Patent Publication No. 2007/0162645 to Han entitled “Communication system for data transfer between on-chip circuits” dated Jul. 12, 2007, U.S. patent application Ser. No. 11/264,956 to Guenin et al. entitled “Structures and methods for proximity communication using bridge chips” dated Nov. 1, 2005, and WO/2005/001928 to Hester et al. entitled “Capacitor-related systems for addressing package/motherboard resonance” dated Jun. 1, 2005. The foregoing patents and patent applications are hereby incorporated by reference herein, each in its respective entirety.